----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:44:31 04/27/2010 
-- Design Name: 
-- Module Name:    sinlut - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sinlookup is
    Port ( CLOCK : in  STD_LOGIC;
           LUT_ADDRESS : in  STD_LOGIC_VECTOR (5 downto 0);
           OUTX : out  STD_LOGIC_VECTOR (15 downto 0));
end sinlookup;

architecture Behavioral of sinlookup is
TYPE t_mem_data IS ARRAY(0 to 511) of std_logic_vector(15 downto 0);

   -- Your program is entered here, as initialization values for
   -- the "mem_data" signal.
   SIGNAL mem_data: t_mem_data :=
	   ( 
		 0 => "0000000000100001",
		 1 => "0000000001000011",
		 2 => "0000000001100011",
		 3 => "0000000010000011",
		 4 => "0000000010100010",
		 5 => "0000000011000000",
		 6 => "0000000011011100",
		 7 => "0000000011110111",
		 8 => "0000000100001111",
		 9 => "0000000100100110",
		 10 => "0000000100111010",
		 11 => "0000000101001100",
		 12 => "0000000101011100",
		 13 => "0000000101101001",
		 14 => "0000000101110011",
		 15 => "0000000101111010",
		 16 => "0000000101111111",
		 17 => "0000000110000000",
		 18 => "1111111111111111",
		 19 => "0000000000000000",
		 20 => "0000000000000001",
		 21 => "0000000000000010",
		 22 => "0000000000000011",
		 23 => "0000000000000100",
		 24 => "0000000000000101",
		 25 => "0000000000000110",
		 26 => "0000000000000111",
		 27 => "0000000000001000",
		 28 => "0000000000001001",
		 29 => "0000000000001010",
		 30 => "0000000000001011",
		 31 => "0000000000001100",
		 32 => "0000000000001101",
		 33 => "0000000000001110",
		 34 => "0000000000001111",

		 others => "0000000000000000"  -- all other memory locations set to 0
			);
begin

RAM_Process: process(CLOCK)
		VARIABLE memaddr : INTEGER RANGE 0 TO 511;
   BEGIN
		IF rising_edge(CLOCK) THEN
		  OUTX <= mem_data(CONV_INTEGER(LUT_ADDRESS));
		END IF;
	END PROCESS;
	
end Behavioral;

